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VTS
1999
IEEE
71views Hardware» more  VTS 1999»
10 years 8 months ago
Test Generation for Ground Bounce in Internal Logic Circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
10 years 8 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
10 years 9 months ago
Understanding and minimizing ground bounce during mode transition of power gating structures
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
ICCD
2000
IEEE
123views Hardware» more  ICCD 2000»
11 years 1 months ago
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
Payam Heydari, Massoud Pedram
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