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CCECE
2011
IEEE
12 years 4 months ago
A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by apply...
Kambiz Nanbakhsh, Hamidreza Maghami, Samad Sheikha...