Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
DSD
2011
IEEE
200views Hardware» more  DSD 2011»
10 years 1 months ago
Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas K...
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
10 years 4 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
IJSNET
2008
118views more  IJSNET 2008»
11 years 1 months ago
Public key cryptography empowered smart dust is affordable
: Public key cryptography (PKC) has been considered for a long time to be computationally too expensive for small battery powered devices. However, PKC turned out to be very benefi...
Steffen Peter, Peter Langendörfer, Krzysztof ...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
11 years 5 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ASPDAC
2006
ACM
125views Hardware» more  ASPDAC 2006»
11 years 7 months ago
ASIP approach for implementation of H.264/AVC
- This paper presents an Application-Specific Instruction Set Processor (ASIP) approach for implementation of H.264/AVC. The proposed ASIP has special instructions for intra predic...
Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung...
IPPS
2006
IEEE
11 years 7 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
11 years 7 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
DDECS
2007
IEEE
102views Hardware» more  DDECS 2007»
11 years 7 months ago
IP Integration Overhead Analysis in System-on-Chip Video Encoder
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. ...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
11 years 10 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
books