Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
CODES
2011
IEEE
10 years 1 months ago
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for tr...
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R....
CORR
2011
Springer
184views Education» more  CORR 2011»
10 years 5 months ago
Decision-Feedback Differential Detection in Impulse-Radio Ultra-Wideband Systems
—Building upon recent approaches for detection of impulse-radio ultra-wideband (IR-UWB) based on compressed sensing (CS), we combine this approach with techniques known from adva...
Andreas Schenk, Robert F. H. Fischer
JCM
2008
118views more  JCM 2008»
11 years 1 months ago
New Receiver Architecture Based on Optical Parallel Interference Cancellation for the Optical CDMA
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
N. Elfadel, A. A. Aziz, E. Idriss, A. Mohammed, N....
MSO
2003
11 years 2 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ASAP
2006
IEEE
124views Hardware» more  ASAP 2006»
11 years 3 months ago
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers
This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. I...
Daesun Oh, Keshab K. Parhi
ARITH
2003
IEEE
11 years 6 months ago
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latenc...
Soonhak Kwon
ISCAS
2006
IEEE
145views Hardware» more  ISCAS 2006»
11 years 7 months ago
The wordlength determination problem of linear time invariant systems with multiple outputs - a geometric programming approach
This paper proposes two new methods for optimizing objectives and constraints. The GP approach is very general and hardware resources in finite wordlength implementation of it allo...
S. C. Chan, K. M. Tsui
books