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ICCD
2005
IEEE
134views Hardware» more  ICCD 2005»
14 years 2 months ago
Architectural Considerations for Energy Efficiency
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
ICCD
2005
IEEE
102views Hardware» more  ICCD 2005»
14 years 2 months ago
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
This paper proposes a response compactor, named ChiYun compactor, to compact scan-out responses in the presence of unknown values. By adding storage elements into an Xor network, ...
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Cha...
ICCD
2005
IEEE
128views Hardware» more  ICCD 2005»
14 years 2 months ago
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits
This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) a...
Li-Kai Chang, Fu-Chiung Cheng
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
14 years 2 months ago
State Set Management for SAT-based Unbounded Model Checking
In recent years, Boolean Satisfiability (SAT) has been shown to hold potential for Unbounded Model Checking (UMC). The success of SAT-based UMC largely relies on (i) the SAT solv...
Kameshwar Chandrasekar, Michael S. Hsiao
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
14 years 2 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
ICCD
2005
IEEE
119views Hardware» more  ICCD 2005»
14 years 2 months ago
Deployment of Better Than Worst-Case Design: Solutions and Needs
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
Todd M. Austin, Valeria Bertacco
ICCD
2005
IEEE
120views Hardware» more  ICCD 2005»
14 years 2 months ago
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhu...
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
14 years 2 months ago
Near-memory Caching for Improved Energy Consumption
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mos...
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
14 years 2 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 2 months ago
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Abstract-- We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and are...
Nathan Sadler, Daniel Sorin