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ASYNC
2015
IEEE
37views Hardware» more  ASYNC 2015»
5 years 7 months ago
Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults
—Asynchronous Networks-on-Chip (NoCs) have been proposed as a promising infrastructure to provide scalable and efficient on-chip communication for many-core systems. Using the Q...
Guangda Zhang, Jim D. Garside, Wei Song 0002, Javi...
ASYNC
2015
IEEE
25views Hardware» more  ASYNC 2015»
5 years 7 months ago
Low Power Monolithic 3D IC Design of Asynchronous AES Core
—In this paper, we demonstrate, for the first time, that a monolithic 3D implementation of an asynchronous AES encryption core can achieve up to 50.3% footprint reduction, 25.7%...
Neela Lohith Penmetsa, Christos Sotiriou, Sung Kyu...
ASYNC
2015
IEEE
29views Hardware» more  ASYNC 2015»
5 years 7 months ago
DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS
—This paper describes DD1, an asynchronous radiation-hard 8-bit AVR R microcontroller (MCU) implemented in TSMC 40LP, a low-power bulk 40nm CMOS process. Designed for extreme rel...
Sean Keller, Alain J. Martin, Chris Moore
ASYNC
2015
IEEE
28views Hardware» more  ASYNC 2015»
5 years 7 months ago
Timing Driven Placement for Quasi Delay-Insensitive Circuits
—Asynchronous circuits offer promise in handling current and future technology scaling challenges. Unfortunately, their impact has been limited by the lack of design automation. ...
Robert Karmazin, Stephen Longfield Jr., Carlos Tad...
ASPDAC
2015
ACM
21views Hardware» more  ASPDAC 2015»
5 years 7 months ago
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies
Abstract—Modern high-speed links and I/O subsystems often employ sophisticated coding strategies to boost error resilience and achieve multiGb/s throughput. The end-to-end analys...
Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhu...
ASPDAC
2015
ACM
27views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Modeling and optimization of low power resonant clock mesh
—Power consumption is becoming more critical in modern integrated circuit (IC) designs and clock network is one of the major contributors for on-chip power. Resonant clock has be...
Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang
ASPDAC
2015
ACM
17views Hardware» more  ASPDAC 2015»
5 years 7 months ago
An HDL-synthesized gated-edge-injection PLL with a current output DAC
– This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for ...
Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot...
ASPDAC
2015
ACM
19views Hardware» more  ASPDAC 2015»
5 years 7 months ago
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations
Abstract—A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In...
Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud...
ASPDAC
2015
ACM
19views Hardware» more  ASPDAC 2015»
5 years 7 months ago
A negative-resistance sense amplifier for low-voltage operating STT-MRAM
- This paper exhibits a 65-NM 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at 0.38V. The proposed sense amplifier comprises a boosted-gate ...
Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shi...
ASPDAC
2015
ACM
27views Hardware» more  ASPDAC 2015»
5 years 7 months ago
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits
Abstract— We address the problem of formally verifying nonlinear analog circuits with an uncertain initial set by computing their reachable set. A reachable set contains the unio...
Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoell...
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