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DFT
1999
IEEE
75views VLSI» more  DFT 1999»
13 years 9 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
13 years 9 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
ATS
2002
IEEE
110views Hardware» more  ATS 2002»
13 years 9 months ago
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for hierarchical test. Based on a cel...
Yiorgos Makris, Alex Orailoglu