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HIPEAC
2005
Springer
9 years 9 months ago
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems
We present and evaluate the TILA-rin GPU microarchitecture for embedded systems using the ATTILA GPU simulation framework. We use a trace from an execution of the Unreal Tournament...
Victor Moya Del Barrio, Carlos González, Jo...
HIPEAC
2005
Springer
9 years 9 months ago
Enhancing Network Processor Simulation Speed with Statistical Input Sampling
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
Jia Yu, Jun Yang 0002, Shaojie Chen, Yan Luo, Laxm...
HIPEAC
2005
Springer
9 years 9 months ago
Memory-Centric Security Architecture
Abstract. This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for ...
Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
HIPEAC
2005
Springer
9 years 9 months ago
Induction Variable Analysis with Delayed Abstractions
ions Sebastian Pop 1 , Albert Cohen 2 , and Georges-Andr´e Silber 1 1 CRI, Mines Paris, Fontainebleau, France 2 ALCHEMY group, INRIA Futurs, Orsay, France Abstract. This paper pre...
Sebastian Pop, Albert Cohen, Georges-André ...
HIPEAC
2005
Springer
9 years 9 months ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli
HIPEAC
2005
Springer
9 years 9 months ago
Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
Bengu Li, Ganesh Venkatesh, Brad Calder, Rajiv Gup...
HIPEAC
2005
Springer
9 years 9 months ago
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations
Detecting and predicting a program’s execution phases are crucial to dynamic optimizations and dynamically adaptable systems. This paper shows that a phase can be associated with...
Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, ...
HIPEAC
2005
Springer
9 years 9 months ago
Arc3D: A 3D Obfuscation Architecture
In DRM domain, the adversary has complete control of the computing node - supervisory privileges along with full physical as well as architectural object observational capabilities...
Mahadevan Gomathisankaran, Akhilesh Tyagi
HIPEAC
2005
Springer
9 years 9 months ago
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multila...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
HIPEAC
2005
Springer
9 years 9 months ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...
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