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HOTI
2005
IEEE
9 years 2 months ago
Performance Characterization of a 10-Gigabit Ethernet TOE
Though traditional Ethernet based network architectures such as Gigabit Ethernet have suffered from a huge performance difference as compared to other high performance networks (e...
Wu-chun Feng, Pavan Balaji, C. Baron, Laxmi N. Bhu...
HOTI
2005
IEEE
9 years 2 months ago
Design and Implementation of a Content-Aware Switch Using a Network Processor
Cluster based server architectures have been widely used as a solution to overloading in web servers because of their cost effectiveness, scalability and reliability. A content aw...
Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. ...
HOTI
2005
IEEE
9 years 2 months ago
Addressing Queuing Bottlenecks at High Speeds
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley
HOTI
2005
IEEE
9 years 2 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
HOTI
2005
IEEE
9 years 2 months ago
A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network
We present SPINet (Scalable Photonic Integrated Network), an optical switching architecture particularly designed for photonic integration. The performance of SPINet-based network...
Assaf Shacham, Benjamin G. Lee, Keren Bergman
HOTI
2005
IEEE
9 years 2 months ago
Control Path Implementation for a Low-Latency Optical HPC Switch
— A crucial part of any high-performance computing system is its interconnection network. In the OSMOSIS project, Corning and IBM are jointly developing a demonstrator interconne...
Cyriel Minkenberg, François Abel, Peter M&u...
HOTI
2005
IEEE
9 years 2 months ago
Internet Infrastructure Security
G. Manimaran, Basheer Al-Duwairi
HOTI
2005
IEEE
9 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
HOTI
2005
IEEE
9 years 2 months ago
A Scalable Switch for Service Guarantees
— Operators need routers to provide service guarantees such as guaranteed flow rates and fairness among flows, so as to support real-time traffic and traffic engineering. How...
Bill Lin, Isaac Keslassy
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