Sciweavers

HPCA
2002
IEEE
13 years 9 months ago
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems
Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configura...
Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
HPCA
2002
IEEE
13 years 9 months ago
Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management
This paper proposes the use of formal feedback control theory as a way to implement adaptive techniques in the processor architecture. Dynamic thermal management (DTM) is used as ...
Kevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan
HPCA
2002
IEEE
13 years 9 months ago
Non-Vital Loads
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...
Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul...
HPCA
2002
IEEE
13 years 9 months ago
User-Level Communication in Cluster-Based Servers
Clusters of commodity computers are currently being used to provide the scalability required by severalpopular Internet services. In this paper we evaluate an efficient cluster-b...
Enrique V. Carrera, Srinath Rao, Liviu Iftode, Ric...
HPCA
2002
IEEE
14 years 4 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
HPCA
2002
IEEE
14 years 4 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
HPCA
2002
IEEE
14 years 4 months ago
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the n...
G. Edward Suh, Srinivas Devadas, Larry Rudolph
HPCA
2002
IEEE
14 years 4 months ago
Improving Value Communication for Thread-Level Speculation
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
HPCA
2002
IEEE
14 years 4 months ago
Modeling Value Speculation
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
Yiannakis Sazeides
HPCA
2002
IEEE
14 years 4 months ago
Bandwidth Adaptive Snooping
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, ...