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HPCA
2006
IEEE
10 years 5 months ago
Speculative synchronization and thread management for fine granularity threads
Performance of multithreaded programs is heavily influenced by the latencies of the thread management and synchronization operations. Improving these latencies becomes especially...
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gr...
HPCA
2006
IEEE
10 years 5 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
HPCA
2006
IEEE
11 years 1 days ago
CMP design space exploration subject to physical constraints
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
Yingmin Li, Benjamin C. Lee, David Brooks, Zhigang...
HPCA
2006
IEEE
11 years 1 days ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
HPCA
2006
IEEE
11 years 1 days ago
High performance file I/O for the Blue Gene/L supercomputer
Parallel I/O plays a crucial role for most data-intensive applications running on massively parallel systems like Blue Gene/L that provides the promise of delivering enormous comp...
Hao Yu, Ramendra K. Sahoo, C. Howson, G. Almasi, J...
HPCA
2006
IEEE
11 years 1 days ago
Phase characterization for power: evaluating control-flow-based and event-counter-based techniques
Computer systems increasingly rely on dynamic, phasebased system management techniques, in which system hardware and software parameters may be altered or tuned at runtime for dif...
Canturk Isci, Margaret Martonosi
HPCA
2006
IEEE
11 years 1 days ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
HPCA
2006
IEEE
11 years 1 days ago
Store vectors for scalable memory dependence prediction and scheduling
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
Samantika Subramaniam, Gabriel H. Loh
HPCA
2006
IEEE
11 years 1 days ago
DMA-aware memory energy management
As increasingly larger memories are used to bridge the widening gap between processor and disk speeds, main memory energy consumption is becoming increasingly dominant. Even thoug...
Vivek Pandey, Weihang Jiang, Yuanyuan Zhou, Ricard...
HPCA
2006
IEEE
11 years 1 days ago
InfoShield: a security architecture for protecting information usage in memory
Cyber theft is a serious threat to Internet security. It is one of the major security concerns by both network service providers and Internet users. Though sensitive information c...
Guofei Gu, Hsien-Hsin S. Lee, Joshua B. Fryman, Ju...
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