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ICCAD
1992
IEEE
96views Hardware» more  ICCAD 1992»
13 years 8 months ago
Configuring multiple scan chains for minimum test time
Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
13 years 8 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
ICCAD
1992
IEEE
153views Hardware» more  ICCAD 1992»
13 years 8 months ago
Efficient techniques for inductance extraction of complex 3-D geometries
In this paper we describe combining a mesh analysis equation formulation technique with a preconditioned GORES matrix solution algorithm to accelerate the determination of inducta...
Mattan Kamon, Michael J. Tsuk, C. Smithhisler, Jac...
ICCAD
1992
IEEE
91views Hardware» more  ICCAD 1992»
13 years 8 months ago
HYPER-LP: a system for power minimization using architectural transformations
Anantha Chandrakasan, Miodrag Potkonjak, Jan M. Ra...
ICCAD
1992
IEEE
148views Hardware» more  ICCAD 1992»
13 years 8 months ago
McPOWER: a Monte Carlo approach to power estimation
Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors and or permanent damage. The severity of the problem increases in proportion to t...
Richard Burch, Farid N. Najm, Ping Yang, Timothy N...
ICCAD
1992
IEEE
137views Hardware» more  ICCAD 1992»
13 years 8 months ago
Equivalent design representations and transformations for interactive scheduling
High-level synthesis (HLS) requires more designer interaction to better meet the needs of experienced designers. However, attempts to create a highly interactive synthesis process...
Roger P. Ang, Nikil D. Dutt