ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
This paper presents a method to characterize Nyquist rate A/D converters based on the use of a first order statistical behavioral model. The proposed model is derived from a very...