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ICCAD
1996
IEEE
86views Hardware» more  ICCAD 1996»
13 years 7 months ago
Tearing based automatic abstraction for CTL model checking
Based Automatic Abstraction for CTL Model Checking Woohyuk Lee Abelardo Pardo Jae-Young Jang Gary Hachtel Fabio Somenzi University of Colorado ECEN Campus Box 425 Boulder, CO, 8030...
Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary ...
ICCAD
1996
IEEE
106views Hardware» more  ICCAD 1996»
13 years 7 months ago
Heterogeneous built-in resiliency of application specific programmable processors
Abstract - Using the exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR p...
Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
ICCAD
1996
IEEE
122views Hardware» more  ICCAD 1996»
13 years 7 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
ICCAD
1996
IEEE
94views Hardware» more  ICCAD 1996»
13 years 7 months ago
Metamorphosis: state assignment by retiming and re-encoding
This paper presents Metamorphosis1
Balakrishnan Iyer, Maciej J. Ciesielski
ICCAD
1996
IEEE
164views Hardware» more  ICCAD 1996»
13 years 7 months ago
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...
Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben ...
ICCAD
1996
IEEE
77views Hardware» more  ICCAD 1996»
13 years 7 months ago
Power optimization in disk-based real-time application specific systems
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
Inki Hong, Miodrag Potkonjak
ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
13 years 7 months ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
ICCAD
1996
IEEE
88views Hardware» more  ICCAD 1996»
13 years 7 months ago
Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
A methodology for hierarchicalstatistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principalcompon...
Eric Felt, Stefano Zanella, Carlo Guardiani, Alber...
ICCAD
1996
IEEE
78views Hardware» more  ICCAD 1996»
13 years 7 months ago
Stratified random sampling for power estimation
Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud P...
ICCAD
1996
IEEE
141views Hardware» more  ICCAD 1996»
13 years 7 months ago
An observability-based code coverage metric for functional simulation
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer