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ICCAD
1997
IEEE
71views Hardware» more  ICCAD 1997»
13 years 8 months ago
Timing analysis based on primitive path delay fault identification
Mukund Sivaraman, Andrzej J. Strojwas
ICCAD
1997
IEEE
84views Hardware» more  ICCAD 1997»
13 years 8 months ago
Global harmony: coupled noise analysis for full-chip RC interconnect networks
Kenneth L. Shepard, Vinod Narayanan, Peter C. Elme...
ICCAD
1997
IEEE
133views Hardware» more  ICCAD 1997»
13 years 8 months ago
Functional simulation using binary decision diagrams
In many veri cation techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams BDDs for functional simulatio...
Christoph Scholl, Rolf Drechsler, Bernd Becker
ICCAD
1997
IEEE
101views Hardware» more  ICCAD 1997»
13 years 8 months ago
NRG: global and detailed placement
We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular...
Majid Sarrafzadeh, Maogang Wang
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
13 years 8 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 8 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
13 years 8 months ago
PRIMA: passive reduced-order interconnect macromodeling algorithm
— This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel ...
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pile...
ICCAD
1997
IEEE
99views Hardware» more  ICCAD 1997»
13 years 8 months ago
High-level area and power estimation for VLSI circuits
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
Mahadevamurty Nemani, Farid N. Najm