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ICCAD
1998
IEEE
117views Hardware» more  ICCAD 1998»
13 years 7 months ago
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
Junwei Hou, Abhijit Chatterjee
ICCAD
1998
IEEE
168views Hardware» more  ICCAD 1998»
13 years 7 months ago
On-line scheduling of hard real-time tasks on variable voltage processor
We consider the problem of scheduling the mixed workload of both sporadic (on-line) and periodic (off-line) tasks on variable voltage processor to optimize power consumption while...
Inki Hong, Miodrag Potkonjak, Mani B. Srivastava
ICCAD
1998
IEEE
130views Hardware» more  ICCAD 1998»
13 years 7 months ago
GPCAD: a tool for CMOS op-amp synthesis
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be fo...
Maria del Mar Hershenson, Stephen P. Boyd, Thomas ...
ICCAD
1998
IEEE
64views Hardware» more  ICCAD 1998»
13 years 7 months ago
Energy-efficiency in presence of deep submicron noise
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
Rajamohana Hegde, Naresh R. Shanbhag
ICCAD
1998
IEEE
112views Hardware» more  ICCAD 1998»
13 years 7 months ago
Using precomputation in architecture and logic resynthesis
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
Soha Hassoun, Carl Ebeling
ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
13 years 7 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ICCAD
1998
IEEE
98views Hardware» more  ICCAD 1998»
13 years 7 months ago
Determination of worst-case aggressor alignment for delay calculation
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...
ICCAD
1998
IEEE
70views Hardware» more  ICCAD 1998»
13 years 7 months ago
Verification by approximate forward and backward reachability
Shankar G. Govindaraju, David L. Dill
ICCAD
1998
IEEE
101views Hardware» more  ICCAD 1998»
13 years 7 months ago
Wireplanning in logic synthesis
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...