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ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
13 years 8 months ago
Symbolic functional and timing verification of transistor-level circuits
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
Clayton B. McDonald, Randal E. Bryant
ICCAD
1999
IEEE
57views Hardware» more  ICCAD 1999»
13 years 8 months ago
Least fixpoint approximations for reachability analysis
In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fab...
ICCAD
1999
IEEE
105views Hardware» more  ICCAD 1999»
13 years 8 months ago
Noise analysis of non-autonomous radio frequency circuits
In this paper we consider the important problem of noise analysis of non-autonomous nonlinear RF circuits in presence of input signal phase noise. We formulate this problem as a s...
Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli
ICCAD
1999
IEEE
181views Hardware» more  ICCAD 1999»
13 years 8 months ago
A new heuristic for rectilinear Steiner trees
The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been ...
Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganle...
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
13 years 8 months ago
Power minimization using system-level partitioning of applications with quality of service requirements
Design systems to provide various quality of service (QoS) guarantees has received a lot of attentions due to the increasing popularity of real-time multimedia and wireless commun...
Gang Qu, Miodrag Potkonjak
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
13 years 8 months ago
Concurrent logic restructuring and placement for timing closure
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...
Jinan Lou, Wei Chen, Massoud Pedram
ICCAD
1999
IEEE
101views Hardware» more  ICCAD 1999»
13 years 8 months ago
Efficient model reduction of interconnect via approximate system gramians
Krylov-subspace based methods for generating low-order models of complicated interconnect are extremely effective, but there is no optimality theory for the resulting models. Alte...
Jing-Rebecca Li, Jacob White
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
13 years 8 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey