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ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
14 years 16 days ago
Whirlpool PLAs: a regular logic structure and their synthesis
 A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
Fan Mo, Robert K. Brayton
ICCAD
2002
IEEE
70views Hardware» more  ICCAD 2002»
14 years 16 days ago
Fast methods for simulation of biomolecule electrostatics
Shihhsien S. Kuo, Michael D. Altman, Jaydeep P. Ba...
ICCAD
2002
IEEE
163views Hardware» more  ICCAD 2002»
14 years 16 days ago
Sub-90nm technologies: challenges and opportunities for CAD
Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practi...
Tanay Karnik, Shekhar Borkar, Vivek De
ICCAD
2002
IEEE
144views Hardware» more  ICCAD 2002»
14 years 16 days ago
Subthreshold leakage modeling and reduction techniques
James Kao, Siva Narendra, Anantha Chandrakasan
ICCAD
2002
IEEE
161views Hardware» more  ICCAD 2002»
14 years 16 days ago
Non-tree routing for reliability and yield improvement
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
ICCAD
2002
IEEE
175views Hardware» more  ICCAD 2002»
14 years 16 days ago
Efficient model order reduction via multi-node moment matching
- The new concept of Multi-node Moment Matching (MMM) is introduced in this paper. The MMM technique simultaneously matches the moments at several nodes of a circuit using explicit...
Yehea I. Ismail
ICCAD
2002
IEEE
87views Hardware» more  ICCAD 2002»
14 years 16 days ago
Schematic-based lumped parameterized behavioral modeling for suspended MEMS
Qi Jing, Tamal Mukherjee, Gary K. Fedder
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 16 days ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ICCAD
2002
IEEE
108views Hardware» more  ICCAD 2002»
14 years 16 days ago
A precorrected-FFT method for simulating on-chip inductance
The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied ...
Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushi...