Sciweavers

ICCAD
2004
IEEE
118views Hardware» more  ICCAD 2004»
14 years 1 months ago
Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization
New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy effic...
Jinfeng Liu, Pai H. Chou
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 1 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He
ICCAD
2004
IEEE
130views Hardware» more  ICCAD 2004»
14 years 1 months ago
Routability-driven placement and white space allocation
In this paper, we present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to re-place cells in order to avoid congested re...
Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, ...
ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
14 years 1 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
14 years 1 months ago
Asymptotic probability extraction for non-normal distributions of circuit performance
While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performanc...
Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawren...
ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
14 years 1 months ago
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...
Jintae Kim, Jaeseo Lee, Lieven Vandenberghe
ICCAD
2004
IEEE
191views Hardware» more  ICCAD 2004»
14 years 1 months ago
Checking consistency of C and Verilog using predicate abstraction and induction
edicate Abstraction and Induction Edmund Clarke Daniel Kroening June 25, 2004 CMU-CS-04-131 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 It is common...
Daniel Kroening, Edmund M. Clarke
ICCAD
2004
IEEE
123views Hardware» more  ICCAD 2004»
14 years 1 months ago
Logical effort based technology mapping
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
Shrirang K. Karandikar, Sachin S. Sapatnekar
ICCAD
2004
IEEE
134views Hardware» more  ICCAD 2004»
14 years 1 months ago
An analytic placer for mixed-size placement and timing-driven placement
We extend the APlace wirelength-driven standard-cell analytic placement framework of [21] to address timing-driven and mixedsize (“boulders and dust”) placement. Compared with...
Andrew B. Kahng, Qinke Wang