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ICCAD
2005
IEEE
71views Hardware» more  ICCAD 2005»
13 years 9 months ago
Simulation-based bug trace minimization with BMC-based refinement
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
13 years 9 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
ICCAD
2005
IEEE
101views Hardware» more  ICCAD 2005»
14 years 15 days ago
FastSies: a fast stochastic integral equation solver for modeling the rough surface effect
In this paper we describe several novel sparsification techniques used in a Fast Stochastic Integral Equation Solver to compute the mean value and the variance of capacitance of ...
Zhenhai Zhu, Jacob K. White
ICCAD
2005
IEEE
97views Hardware» more  ICCAD 2005»
14 years 15 days ago
DiCER: distributed and cost-effective redundancy for variation tolerance
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...
ICCAD
2005
IEEE
94views Hardware» more  ICCAD 2005»
14 years 15 days ago
Post-placement voltage island generation under performance requirement
High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is prop...
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wan...
ICCAD
2005
IEEE
90views Hardware» more  ICCAD 2005»
14 years 15 days ago
Scalable compositional minimization via static analysis
State-equivalence based reduction techniques, e.g. bisimulation minimization, can be used to reduce a state transition system to facilitate subsequent verification tasks. However...
Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 15 days ago
FPGA device and architecture evaluation considering process variations
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...
Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
ICCAD
2005
IEEE
145views Hardware» more  ICCAD 2005»
14 years 15 days ago
Noise margin analysis for dynamic logic circuits
Suwen Yang, Mark R. Greenstreet
ICCAD
2005
IEEE
105views Hardware» more  ICCAD 2005»
14 years 15 days ago
Weighted control scheduling
Abstract — This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. S...
Aravind Vijayakumar, Forrest Brewer