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ICCAD
2007
IEEE
119views Hardware» more  ICCAD 2007»
9 years 3 months ago
IntSim: A CAD tool for optimization of multilevel interconnect networks
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffre...
ICCAD
2007
IEEE
165views Hardware» more  ICCAD 2007»
9 years 5 months ago
Automated refinement checking of concurrent systems
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
ICCAD
2007
IEEE
165views Hardware» more  ICCAD 2007»
9 years 5 months ago
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips
Due to the recent advances in microfluidics, digital microfluidic biochips are expected to revolutionize laboratory procedures. One critical problem for biochip synthesis is the dr...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
ICCAD
2007
IEEE
134views Hardware» more  ICCAD 2007»
9 years 5 months ago
Efficient decoupling capacitance budgeting considering operation and process variations
This paper solves the variation-aware on-chip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worst-case current load, we develop a novel stocha...
Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He
ICCAD
2007
IEEE
234views Hardware» more  ICCAD 2007»
9 years 5 months ago
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Abstract: Polynomial computations over fixed-size bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositi...
Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon ...
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
9 years 5 months ago
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...
Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu ...
ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
9 years 5 months ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
ICCAD
2007
IEEE
91views Hardware» more  ICCAD 2007»
9 years 5 months ago
Sizing and placement of charge recycling transistors in MTCMOS circuits
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
ICCAD
2007
IEEE
107views Hardware» more  ICCAD 2007»
9 years 7 months ago
Formal verification at higher levels of abstraction
velsofAbstraction DanielKroening,OxfordUniversity SanjitA.Seshia,UCBerkeley ICCADTutorial November8,2007
Daniel Kroening, Sanjit A. Seshia
ICCAD
2007
IEEE
100views Hardware» more  ICCAD 2007»
9 years 7 months ago
Parallel domain decomposition for simulation of large-scale power grids
This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-ov...
Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. So...
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