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ICCAD
2007
IEEE
86views Hardware» more  ICCAD 2007»
9 years 11 months ago
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
—During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. In this paper, we introduce several important properties of the s...
Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-C...
ICCAD
2007
IEEE
105views Hardware» more  ICCAD 2007»
9 years 11 months ago
ECO timing optimization using spare cells
(Chinese)
Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
ICCAD
2007
IEEE
108views Hardware» more  ICCAD 2007»
9 years 11 months ago
Novel wire density driven full-chip routing for CMP variation control
— As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling ...
Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-...
ICCAD
2007
IEEE
110views Hardware» more  ICCAD 2007»
9 years 11 months ago
A hybrid scheme for compacting test responses with unknown values
This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature R...
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon W...
ICCAD
2007
IEEE
99views Hardware» more  ICCAD 2007»
9 years 11 months ago
Automating post-silicon debugging and repair
Modern IC designs have reached unparalleled levels of complexity, resulting in more and more bugs discovered after design tape-out However, so far only very few EDA tools for post...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ICCAD
2007
IEEE
87views Hardware» more  ICCAD 2007»
9 years 11 months ago
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
Philip Brisk, Ajay K. Verma, Paolo Ienne
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
9 years 11 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
9 years 11 months ago
Remote activation of ICs for piracy prevention and digital right management
— We introduce a remote activation scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy. Remote activation enables designers to lock eac...
Yousra Alkabani, Farinaz Koushanfar, Miodrag Potko...
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
9 years 11 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
ICCAD
2007
IEEE
122views Hardware» more  ICCAD 2007»
9 years 11 months ago
Engineering change using spare cells with constant insertion
—In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referre...
Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgo...
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