ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale designs. Monte Carlo methods are universally employed to validate the accuracy of the appr...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— In this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient VFI (Voltage-Frequency Island) based Network-on-Chip. Unlike the rece...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
—This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifie...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
—We present in this paper a fast and stable global router called NTHU-Route 2.0 that improves the solution quality and runtime of a state-of-the-art router, NTHU-Route, by the fo...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for ...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—Buffer resizing and buffer insertion are two transformation techniques for the performance optimization of elastic systems. Different approaches for each technique have ...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...