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ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
9 years 4 months ago
The synthesis of combinational logic to generate probabilities
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
Weikang Qian, Marc D. Riedel, Kia Bazargan, David ...
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
9 years 4 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu
ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
9 years 4 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ICCAD
2009
IEEE
126views Hardware» more  ICCAD 2009»
9 years 4 months ago
Timing Arc based logic analysis for false noise reduction
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum...
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
9 years 4 months ago
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction
With the adoption of ultra regular fabric paradigms for controlling design printability at the 22nm node and beyond, there is an emerging need for a layout-driven, pattern-based p...
Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Dani...
ICCAD
2009
IEEE
98views Hardware» more  ICCAD 2009»
9 years 4 months ago
GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems
A generalized Hamiltonian method (GHM) is proposed for passivity test of descriptor systems (DSs) which describe impedance or admittance input-output responses. GHM can test passi...
Zheng Zhang, Chi-Un Lei, Ngai Wong
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
9 years 4 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
ICCAD
2009
IEEE
89views Hardware» more  ICCAD 2009»
9 years 4 months ago
Decoupling capacitance efficient placement for reducing transient power supply noise
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource...
Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. T...
ICCAD
2009
IEEE
131views Hardware» more  ICCAD 2009»
9 years 4 months ago
Scheduling with soft constraints
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
Jason Cong, Bin Liu, Zhiru Zhang
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
9 years 4 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
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