Sciweavers

Share
ICCAD
2009
IEEE
109views Hardware» more  ICCAD 2009»
9 years 4 months ago
Energy reduction for STT-RAM using early write termination
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang
ICCAD
2009
IEEE
123views Hardware» more  ICCAD 2009»
9 years 4 months ago
Multi-level clustering for clock skew optimization
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
Jonas Casanova, Jordi Cortadella
ICCAD
2009
IEEE
135views Hardware» more  ICCAD 2009»
9 years 4 months ago
Enhanced reliability-aware power management through shared recovery technique
While Dynamic Voltage Scaling (DVS) remains as a popular energy management technique for real-time embedded applications, recent research has identified significant and negative i...
Baoxian Zhao, Hakan Aydin, Dakai Zhu
ICCAD
2009
IEEE
96views Hardware» more  ICCAD 2009»
9 years 4 months ago
PSTA-based branch and bound approach to the silicon speedpath isolation problem
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ICCAD
2009
IEEE
106views Hardware» more  ICCAD 2009»
9 years 4 months ago
An efficient pre-assignment routing algorithm for flip-chip designs
The flip-chip package is introduced for modern IC designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing pr...
Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fan...
ICCAD
2009
IEEE
92views Hardware» more  ICCAD 2009»
9 years 4 months ago
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
ICCAD
2009
IEEE
88views Hardware» more  ICCAD 2009»
9 years 4 months ago
IPR: In-Place Reconfiguration for FPGA fault tolerance
Zhe Feng 0002, Yu Hu, Lei He, Rupak Majumdar
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
9 years 4 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
9 years 4 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
books