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ICCD
1995
IEEE
95views Hardware» more  ICCD 1995»
13 years 8 months ago
Caching processor general registers
Robert Yung, Neil C. Wilhelm
ICCD
1995
IEEE
85views Hardware» more  ICCD 1995»
13 years 8 months ago
A high-performance asynchronous SCSI controller
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
Kenneth Y. Yun, David L. Dill
ICCD
1995
IEEE
100views Hardware» more  ICCD 1995»
13 years 8 months ago
Transformation of min-max optimization to least-square estimation and application to interconnect design optimization
This paper describes a novel approach to nd a tighter bound of the transformation of the Min-Max problems into the one of Least-Square Estimation. It is well known that the above ...
Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
ICCD
1995
IEEE
100views Hardware» more  ICCD 1995»
13 years 8 months ago
A coprocessor for accurate and reliable numerical computations
Michael J. Schulte, Earl E. Swartzlander Jr.
ICCD
1995
IEEE
121views Hardware» more  ICCD 1995»
13 years 8 months ago
Analysis of conditional resource sharing using a guard-based control representation
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of through...
Ivan P. Radivojevic, Forrest Brewer
ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
13 years 8 months ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
ICCD
1995
IEEE
83views Hardware» more  ICCD 1995»
13 years 8 months ago
Concurrent timing optimization of latch-based digital systems
Many design techniques have been proposed to optimize the performance of a digital system implemented in a given technology. Each of these techniques can be advantageous in partic...
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C...
ICCD
1995
IEEE
51views Hardware» more  ICCD 1995»
13 years 8 months ago
Implementing a STARI chip
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a...
Mark R. Greenstreet
ICCD
1995
IEEE
109views Hardware» more  ICCD 1995»
13 years 8 months ago
Verifying the performance of the PCI local bus using symbolic techniques
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
Sérgio Vale Aguiar Campos, Edmund M. Clarke...