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ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 1 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
14 years 1 months ago
A Minimal Dual-Core Speculative Multi-Threading Architecture
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman...
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 1 months ago
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
Vassos Soteriou, Li-Shiuan Peh
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 1 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
ICCD
2004
IEEE
123views Hardware» more  ICCD 2004»
14 years 1 months ago
Compiler-Based Frame Formation for Static Optimization
We selectively generate and optimize the frames constructed by the rePLay architecture statically. Since static analysis provides a global view of the interaction between the basi...
Feng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorg...
ICCD
2004
IEEE
104views Hardware» more  ICCD 2004»
14 years 1 months ago
Exploiting Quiescent States in Register Lifetime
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...
Rama Sangireddy, Arun K. Somani
ICCD
2004
IEEE
148views Hardware» more  ICCD 2004»
14 years 1 months ago
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures
In this paper, we investigate the core-switch mapping(CSM) problem that optimally maps cores onto an NoC architecture such that either the energy consumption or the congestion is ...
Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha
ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
14 years 1 months ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
14 years 1 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...
ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
14 years 1 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi