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ICCD
2007
IEEE
149views Hardware» more  ICCD 2007»
11 years 3 months ago
A radix-10 SRT divider based on alternative BCD codings
In this paper we present the algorithm and architecture of a radix-10 floating-point divider based on an SRT nonrestoring digit-by-digit algorithm. The algorithm uses conventional...
Álvaro Vázquez, Elisardo Antelo, Pao...
ICCD
2007
IEEE
140views Hardware» more  ICCD 2007»
11 years 3 months ago
Continual hashing for efficient fine-grain state inconsistency detection
Transaction-level modeling (TLM) allows a designer to save functional verification effort during the modular refinement of an SoC by reusing the prior implementation of a module a...
Jae W. Lee, Myron King, Krste Asanovic
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
11 years 3 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...
ICCD
2007
IEEE
150views Hardware» more  ICCD 2007»
11 years 3 months ago
CAP: Criticality analysis for power-efficient speculative multithreading
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
James Tuck, Wei Liu, Josep Torrellas
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
11 years 3 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad
ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
11 years 3 months ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
11 years 3 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
11 years 3 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
ICCD
2007
IEEE
106views Hardware» more  ICCD 2007»
11 years 3 months ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in moder...
Eric L. Hill, Mikko H. Lipasti
ICCD
2007
IEEE
182views Hardware» more  ICCD 2007»
11 years 6 months ago
Reducing leakage power in peripheral circuits of L2 caches
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
Houman Homayoun, Alexander V. Veidenbaum
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