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IEEEPACT
1998
IEEE
13 years 8 months ago
Scanning Polyhedra without Do-loops
We study in this paper the problem of polyhedron scanning which appears for example when generating code for transformed loop nests in automatic parallelization. After a review of...
Pierre Boulet, Paul Feautrier
IEEEPACT
1998
IEEE
13 years 8 months ago
Static Methods in Hybrid Branch Prediction
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...
Dirk Grunwald, Donald C. Lindsay, Benjamin G. Zorn
IEEEPACT
1998
IEEE
13 years 8 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
IEEEPACT
1998
IEEE
13 years 8 months ago
Data Dependence Analysis of Assembly Code
Determination of data dependences is a task typically performed with high-level language source code in today's optimizing and parallelizing compilers. Very little work has b...
Wolfram Amme, Peter Braun, Eberhard Zehendner, Fra...
IEEEPACT
1998
IEEE
13 years 8 months ago
Adaptive Scheduling of Computations and Communications on Distributed Memory Systems
Compile-time scheduling is one approach to extract parallelism which has proved effective when the execution behavior is predictable. Unfortunately, the performance of most priori...
Mayez A. Al-Mouhamed, Homam Najjari
IEEEPACT
1998
IEEE
13 years 8 months ago
Origin 2000 Design Enhancements for Communication Intensive Applications
The SGI Origin 2000 is designedto support a wide range of applications and has low local and remote memory latencies. However, it often has a high ratio of remote to local misses....
Gheith A. Abandah, Edward S. Davidson
IEEEPACT
1998
IEEE
13 years 8 months ago
A Matrix-Based Approach to the Global Locality Optimization Problem
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...