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IEEEPACT
2002
IEEE
10 years 2 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
IEEEPACT
2002
IEEE
10 years 2 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
IEEEPACT
2002
IEEE
10 years 2 months ago
Quantifying Instruction Criticality
Information about instruction criticality can be used to control the application of micro-architectural resources efficiently. To this end, several groups have proposed methods t...
Eric Tune, Dean M. Tullsen, Brad Calder
IEEEPACT
2002
IEEE
10 years 2 months ago
Just-In-Time Java? Compilation for the Itanium® Processor
Tatiana Shpeisman, Guei-Yuan Lueh, Ali-Reza Adl-Ta...
IEEEPACT
2002
IEEE
10 years 2 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
IEEEPACT
2002
IEEE
10 years 2 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
IEEEPACT
2002
IEEE
10 years 2 months ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...
IEEEPACT
2002
IEEE
10 years 2 months ago
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
Soner Önder
IEEEPACT
2002
IEEE
10 years 2 months ago
Predicting Conditional Branches With Fusion-Based Hybrid Predictors
Researchers have studied hybrid branch predictors that leverage the strengths of multiple stand-alone predictors. The common theme among the proposed techniques is a selection mec...
Gabriel H. Loh, Dana S. Henry
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