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IEEEPACT
2005
IEEE
13 years 10 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
IEEEPACT
2005
IEEE
13 years 10 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
IEEEPACT
2005
IEEE
13 years 10 months ago
An Event-Driven Multithreaded Dynamic Optimization Framework
Dynamic optimization has the potential to adapt the program’s behavior at run-time to deliver performance improvements over static optimization. Dynamic optimization systems usu...
Weifeng Zhang, Brad Calder, Dean M. Tullsen
IEEEPACT
2005
IEEE
13 years 10 months ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
IEEEPACT
2005
IEEE
13 years 10 months ago
Store-Ordered Streaming of Shared Memory
Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming prov...
Thomas F. Wenisch, Stephen Somogyi, Nikolaos Harda...
IEEEPACT
2005
IEEE
13 years 10 months ago
Extended Whole Program Paths
We describe the design, generation and compression of the extended whole program path (eWPP) representation that not only captures the control flow history of a program execution...
Sriraman Tallam, Rajiv Gupta, Xiangyu Zhang
IEEEPACT
2005
IEEE
13 years 10 months ago
Parallel Programming and Parallel Abstractions in Fortress
llel Abstractions in Fortress Guy Steele Sun Microsystems Laboratories April 24, 2006
Guy L. Steele Jr.
IEEEPACT
2005
IEEE
13 years 10 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
IEEEPACT
2005
IEEE
13 years 10 months ago
Memory State Compressors for Giga-Scale Checkpoint/Restore
We propose a checkpoint store compression method for coarse-grain giga-scale checkpoint/restore. This mechanism can be useful for debugging, post-mortem analysis and error recover...
Andreas Moshovos, Alexandros Kostopoulos