Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
IEEEPACT
2007
IEEE
12 years 5 months ago
Call-chain Software Instruction Prefetching in J2EE Server Applications
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...
Priya Nagpurkar, Harold W. Cain, Mauricio J. Serra...
IEEEPACT
2007
IEEE
12 years 5 months ago
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Mo...
IEEEPACT
2007
IEEE
12 years 5 months ago
FAME: FAirly MEasuring Multithreaded Architectures
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
Javier Vera, Francisco J. Cazorla, Alex Pajuelo, O...
IEEEPACT
2007
IEEE
12 years 5 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
IEEEPACT
2007
IEEE
12 years 5 months ago
Fast Track: Supporting Unsafe Optimizations with Software Speculation
The use of multi-core, multi-processor machines is opening new opportunities for software speculation, where program code is speculatively executed to improve performance at the a...
Kirk Kelsey, Chengliang Zhang, Chen Ding
IEEEPACT
2007
IEEE
12 years 5 months ago
Speculative Decoupled Software Pipelining
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of paralle...
Neil Vachharajani, Ram Rangan, Easwaran Raman, Mat...
IEEEPACT
2007
IEEE
12 years 5 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
IEEEPACT
2007
IEEE
12 years 5 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
IEEEPACT
2007
IEEE
12 years 5 months ago
Unified Architectural Support for Soft-Error Protection or Software Bug Detection
In this paper we propose a unified architectural support that can be used flexibly for either soft-error protection or software bug detection. Our approach is based on dynamically...
Martin Dimitrov, Huiyang Zhou
books