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IISWC
2008
IEEE
9 years 10 months ago
Implications of cache asymmetry on server consolidation performance
Padma Apparao, Ravi R. Iyer, Donald Newell
IISWC
2008
IEEE
9 years 10 months ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
IISWC
2008
IEEE
9 years 10 months ago
On the representativeness of embedded Java benchmarks
— Java has become one of the predominant languages for embedded and mobile platforms due to its architecturally neutral design, portability, and security. But Java execution in t...
Ciji Isen, Lizy Kurian John, Jung Pil Choi, Hyo Ju...
IISWC
2008
IEEE
9 years 10 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood
IISWC
2008
IEEE
9 years 10 months ago
Workload characterization of selected JEE-based Web 2.0 applications
Web 2.0 represents the evolution of the web from a source of information to a platform. Network advances have permitted users to migrate from desktop applications to so-called Ric...
Priya Nagpurkar, William Horn, U. Gopalakrishnan, ...
IISWC
2008
IEEE
9 years 10 months ago
PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors
The PARSEC benchmark suite was recently released and has been adopted by a significant number of users within a short amount of time. This new collection of workloads is not yet ...
Christian Bienia, Sanjeev Kumar, Kai Li
IISWC
2008
IEEE
9 years 10 months ago
Reproducible simulation of multi-threaded workloads for architecture design exploration
As multiprocessors become mainstream, techniques to address efficient simulation of multi-threaded workloads are needed. Multi-threaded simulation presents a new challenge: non-d...
Cristiano Pereira, Harish Patil, Brad Calder
IISWC
2008
IEEE
9 years 10 months ago
STAMP: Stanford Transactional Applications for Multi-Processing
Abstract—Transactional Memory (TM) is emerging as a promising technology to simplify parallel programming. While several TM systems have been proposed in the research literature,...
Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, ...
IISWC
2008
IEEE
9 years 10 months ago
Can hardware performance counters be trusted?
Vincent M. Weaver, Sally A. McKee
IISWC
2008
IEEE
9 years 10 months ago
Empirical examination of a collaborative web application
Christopher Stewart, Matthew Leventi, Kai Shen
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