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    ASPDAC
    2012
    ACM
    241views Hardware» more  ASPDAC 2012»
    On error modeling of electrical bugs for post-silicon timing validation
    12 years 16 days ago
    On error modeling of electrical bugs for post-silicon timing validation
    Download  cadlab.ece.ucsb.edu
    —There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timi...
    Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing...
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