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ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 1 months ago
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jia...