Sciweavers

DAC
1996
ACM
13 years 9 months ago
Post-Layout Optimization for Deep Submicron Design
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emu...