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ERSA
2009
185views Hardware» more  ERSA 2009»
9 years 7 days ago
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
Mariusz Grad, Christian Plessl
CASES
2010
ACM
9 years 14 days ago
Fine-grain dynamic instruction placement for L0 scratch-pad memory
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
JongSoo Park, James D. Balfour, William J. Dally
TVLSI
2002
102views more  TVLSI 2002»
9 years 2 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
TCAD
2002
104views more  TCAD 2002»
9 years 2 months ago
An instruction-level energy model for embedded VLIW architectures
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
CE
2005
74views more  CE 2005»
9 years 2 months ago
PowerPoint's power in the classroom: enhancing students' self-efficacy and attitudes
The current study examined the effects of non-interactive computer assisted instruction on students
Joshua E. Susskind
IJLT
2007
67views more  IJLT 2007»
9 years 2 months ago
Differentiated e-learning: five approaches through instructional technology
: Differentiated instruction is an approach to teaching that acknowledges people have multiple paths for learning and for making sense of ideas. In e-learning, differentiated instr...
Kathleen Scalise
MICRO
2006
IEEE
107views Hardware» more  MICRO 2006»
9 years 2 months ago
Dataflow Predication
Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order microarchitecture...
Aaron Smith, Ramadass Nagarajan, Karthikeyan Sanka...
MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
9 years 2 months ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
JCP
2008
118views more  JCP 2008»
9 years 2 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
CJ
2006
84views more  CJ 2006»
9 years 2 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
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