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MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
11 years 5 months ago
An integrated approach to accelerate data and predicate computations in hyperblocks
To exploit increased instruction-level parallelism available in modern processors, we describe the formation and optimization of tracenets, an integrated approach to reducing the ...
Alexandre E. Eichenberger, Waleed Meleis, Suman Ma...
PLDI
1995
ACM
11 years 9 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
MICRO
1995
IEEE
217views Hardware» more  MICRO 1995»
11 years 9 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Jack W. Davidson, Sanjay Jinturkar
ARC
2007
Springer
150views Hardware» more  ARC 2007»
11 years 9 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
SC
1992
ACM
11 years 9 months ago
Compiler Code Transformations for Superscalar-Based High Performance Systems
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
Scott A. Mahlke, William Y. Chen, John C. Gyllenha...
HPCN
1998
Springer
11 years 9 months ago
Evaluation of Two Compiler-Based Approaches for the Parallelisation of an MPEG-2 Decoder
In this paper, we evaluate two different approaches for the compiler-based parallelisation of a C program for MPEG-2 decoding. The first approach experiments with a commercial auto...
Arnaud Laffitte, Rizos Sakellariou, John R. Gurd
ASPLOS
1998
ACM
11 years 9 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
11 years 9 months ago
Analytic Evaluation of Shared-memory Systems with ILP Processors
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mar...
HPCA
1998
IEEE
11 years 9 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
ICPP
2005
IEEE
11 years 11 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
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