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CAL
2008
13 years 4 months ago
Hierarchical Instruction Register Organization
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and ...
David Black-Schaffer, James D. Balfour, William J....
HUC
2010
Springer
13 years 4 months ago
Augmenting on-screen instructions with micro-projected guides: when it works, and when it fails
We present a study that evaluates the effectiveness of augmenting on-screen instructions with micro-projection for manual task guidance unlike prior work, which replaced screen in...
Stephanie Rosenthal, Shaun K. Kane, Jacob O. Wobbr...
DYNAMO
2000
87views more  DYNAMO 2000»
13 years 5 months ago
Derive: a tool that automatically reverse-engineers instruction encodings
Many binary tools, such as disassemblers, dynamiccode generation systems, and executable code rewriters, need to understand how machine instructions are encoded. Unfortunately, sp...
Dawson R. Engler, Wilson C. Hsieh
USAB
2008
13 years 5 months ago
Instruction Formats and Navigation Aids in Mobile Devices
Three different instruction formats were examined respecting their usefulness for the navigation through hierarchical menus in mobile phones. 56 middle-aged adults had to solve fou...
Martina Ziefle
ITS
2010
Springer
145views Multimedia» more  ITS 2010»
13 years 6 months ago
Predictors of Transfer of Experimental Design Skills in Elementary and Middle School Children
A vital goal of instruction is to enable learners to transfer acquired knowledge to appropriate future situations. For elementary school children in middle-high-SES schools, “exp...
Stephanie Siler, David Klahr, Cressida Magaro, Kev...
HPCA
1995
IEEE
13 years 8 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
ASPLOS
2006
ACM
13 years 8 months ago
Instruction scheduling for a tiled dataflow architecture
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
CAV
2010
Springer
153views Hardware» more  CAV 2010»
13 years 8 months ago
There's Plenty of Room at the Bottom: Analyzing and Verifying Machine Code
This paper discusses the obstacles that stand in the way of doing a good job of machine-code analysis. Compared with analysis of source code, the challenge is to drop all assumptio...
Thomas W. Reps, Junghee Lim, Aditya V. Thakur, Gog...
CASES
2007
ACM
13 years 8 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
13 years 8 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain