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MICRO
1997
IEEE
87views Hardware» more  MICRO 1997»
13 years 8 months ago
Improving Code Density Using Compression Techniques
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces commo...
Charles Lefurgy, Peter L. Bird, I-Cheng K. Chen, T...
ISCA
1997
IEEE
114views Hardware» more  ISCA 1997»
13 years 8 months ago
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
Sriram Vajapeyam, Tulika Mitra
ISCA
1998
IEEE
107views Hardware» more  ISCA 1998»
13 years 8 months ago
Memory Dependence Prediction Using Store Sets
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
George Z. Chrysos, Joel S. Emer
IEEEPACT
1998
IEEE
13 years 8 months ago
Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad...
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 8 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 8 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
HPCA
1999
IEEE
13 years 8 months ago
Instruction Recycling on a Multiple-Path Processor
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
Steven Wallace, Dean M. Tullsen, Brad Calder
CADE
2000
Springer
13 years 8 months ago
Machine Instruction Syntax and Semantics in Higher Order Logic
Abstract. Proof-carrying code and other applications in computer security require machine-checkable proofs of properties of machine-language programs. These in turn require axioms ...
Neophytos G. Michael, Andrew W. Appel
ISPAN
2000
IEEE
13 years 9 months ago
Comprehensive Evaluation of an Instruction Reissue Mechanism
In this paper, we evaluate a mechanism to reissue instructions on the mispredicted speculation path. An instruction which is once dispatched to a functional unit during mispredict...
Toshinori Sato, Itsujiro Arita
ASAP
2000
IEEE
141views Hardware» more  ASAP 2000»
13 years 9 months ago
Bit Permutation Instructions for Accelerating Software Cryptography
Permutation is widely used in cryptographic algorithms. However, it is not well-supported in existing instruction sets. In this paper, two instructions, PPERM3R and GRP, are propo...
Zhijie Shi, Ruby B. Lee