Sciweavers

TVLSI
2010
12 years 11 months ago
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...
Hai Lin, Yunsi Fei, Xuan Guan, Zhijie Jerry Shi
IPPS
2010
IEEE
13 years 1 months ago
A low cost split-issue technique to improve performance of SMT clustered VLIW processors
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...
Manoj Gupta, Fermín Sánchez, Josep L...
ICPP
2009
IEEE
13 years 2 months ago
Thread Merging Schemes for Multithreaded Clustered VLIW Processors
Several multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is ...
Manoj Gupta, Fermín Sánchez, Josep L...
SIGDIAL
2010
13 years 2 months ago
Comparing Spoken Language Route Instructions for Robots across Environment Representations
Spoken language interaction between humans and robots in natural environments will necessarily involve communication about space and distance. The current study examines people�...
Matthew Marge, Alexander I. Rudnicky
MICRO
2010
IEEE
134views Hardware» more  MICRO 2010»
13 years 2 months ago
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
Guoping Long, Diana Franklin, Susmit Biswas, Pablo...
TC
2002
13 years 4 months ago
On Augmenting Trace Cache for High-Bandwidth Value Prediction
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
Sang Jeong Lee, Pen-Chung Yew
CAL
2005
13 years 4 months ago
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
TCAD
2008
118views more  TCAD 2008»
13 years 4 months ago
CHIPS: Custom Hardware Instruction Processor Synthesis
This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critica...
Kubilay Atasu, Can C. Özturan, Günhan D&...
CORR
2007
Springer
108views Education» more  CORR 2007»
13 years 4 months ago
Instruction sequences with indirect jumps
We study sequential programs that are instruction sequences with direct and indirect jump instructions. The intuition is that indirect jump instructions are jump instructions wher...
Jan A. Bergstra, C. A. Middelburg
ACL
2006
13 years 6 months ago
Semantic Discourse Segmentation and Labeling for Route Instructions
In order to build a simulated robot that accepts instructions in unconstrained natural language, a corpus of 427 route instructions was collected from human subjects in the office...
Nobuyuki Shimizu