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FPL
2004
Springer
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13 years 10 months ago
BIST Based Interconnect Fault Location for FPGAs
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
Nicola Campregher, Peter Y. K. Cheung, Milan Vasil...