ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Abstract— Frequency dependent interconnect analysis is challenging since lumped equivalent circuit models extracted at different frequencies exhibit distinct time and frequency d...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
CCGRID
2001
IEEE
13 years 8 months ago
2001
IEEE
This paper describes the principles of an original adaptive interconnect for a computational cluster. Torus topology (2d or 3d) is used as a basis but nodes are allowed to effecti...
CF
2007
ACM
13 years 8 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 8 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these sy...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...