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ANCS
2009
ACM
11 years 6 months ago
Motivating future interconnects: a differential measurement analysis of PCI latency
Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and ...
David J. Miller, Philip M. Watts, Andrew W. Moore
ET
2002
85views more  ET 2002»
11 years 8 months ago
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
Mehrdad Nourani, Amir Attarha
CDES
2006
100views Hardware» more  CDES 2006»
11 years 9 months ago
Integrity and Integration Issues for Nano-Tube Based Interconnect Systems
: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
Tulin Mangir
FPL
2006
Springer
96views Hardware» more  FPL 2006»
11 years 11 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
12 years 15 days ago
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L....
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
12 years 1 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
IEEEPACT
2002
IEEE
12 years 1 months ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...
VTS
2003
IEEE
95views Hardware» more  VTS 2003»
12 years 1 months ago
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
DATE
2003
IEEE
76views Hardware» more  DATE 2003»
12 years 1 months ago
Modeling and Evaluation of Substrate Noise Induced by Interconnects
Interconnects have deserved attention as a source of crosstalk to other interconnects, but have been ignored as a source of substrate noise. In this paper, we evaluate the importa...
Ferran Martorell, Diego Mateo, Xavier Aragon&egrav...
VTS
2006
IEEE
122views Hardware» more  VTS 2006»
12 years 2 months ago
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
Vishal Suthar, Shantanu Dutt
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