Sciweavers

Share
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
9 years 29 days ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
ISCA
1998
IEEE
135views Hardware» more  ISCA 1998»
9 years 29 days ago
Branch Prediction Based on Universal Data Compression Algorithms
Data compression and prediction are closely related. Thus prediction methods based on data compression algorithms have been suggested for the branch prediction problem. In this wo...
Eitan Federovsky, Meir Feder, Shlomo Weiss
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
9 years 1 months ago
Alternative Implementations of Two-Level Adaptive Branch Prediction
As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the...
Tse-Yu Yeh, Yale N. Patt
ISCA
1998
IEEE
124views Hardware» more  ISCA 1998»
9 years 1 months ago
Threaded Multiple Path Execution
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...
Steven Wallace, Brad Calder, Dean M. Tullsen
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
9 years 1 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
ISCA
1998
IEEE
117views Hardware» more  ISCA 1998»
9 years 1 months ago
Increasing TLB Reach Using Superpages Backed by Shadow Memory
Mark R. Swanson, Leigh Stoller, John B. Carter
ISCA
1998
IEEE
113views Hardware» more  ISCA 1998»
9 years 1 months ago
Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors
Vijayaraghavan Soundararajan, Mark Heinrich, Ben V...
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
9 years 1 months ago
Analytic Evaluation of Shared-memory Systems with ILP Processors
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mar...
ISCA
1998
IEEE
122views Hardware» more  ISCA 1998»
9 years 1 months ago
Multiscalar Processors
Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykuma...
ISCA
1998
IEEE
155views Hardware» more  ISCA 1998»
9 years 1 months ago
A Study of Branch Prediction Strategies
In high-performance computer systems, performance losses due to conditional branch instructions can be minimized by predicting a branch outcome and fetching, decoding, and/or issu...
James E. Smith
books