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ISCA
2002
IEEE
141views Hardware» more  ISCA 2002»
8 years 11 months ago
SADL: Simulation Architecture Description Language
This paper introduces the Simulation Architecture Description Language (SADL) developed at the National Aeronautics and Space Administration's Marshall Space Flight Center to...
Kenneth G. Ricks, John M. Weirs, B. Earl Wells
ISCA
2002
IEEE
174views Hardware» more  ISCA 2002»
8 years 11 months ago
Efficient Task Partitioning Algorithms for Distributed Shared Memory Systems
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
Sibabrata Ray, Hong Jiang
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
8 years 11 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
9 years 4 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
9 years 4 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
9 years 4 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
9 years 4 months ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
9 years 4 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
9 years 4 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
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