Sciweavers

ISCA
2005
IEEE
117views Hardware» more  ISCA 2005»
13 years 10 months ago
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
Amir Roth
ISCA
2005
IEEE
79views Hardware» more  ISCA 2005»
13 years 10 months ago
Design and Evaluation of Hybrid Fault-Detection Systems
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
ISCA
2005
IEEE
101views Hardware» more  ISCA 2005»
13 years 10 months ago
Virtualizing Transactional Memory
Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, ...
Ravi Rajwar, Maurice Herlihy, Konrad K. Lai
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
13 years 10 months ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt
ISCA
2005
IEEE
81views Hardware» more  ISCA 2005»
13 years 10 months ago
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performa...
Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeve...
ISCA
2005
IEEE
131views Hardware» more  ISCA 2005»
13 years 10 months ago
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging
Significant time is spent by companies trying to reproduce and fix the bugs that occur for released code. To assist developers, we propose the BugNet architecture to continuousl...
Satish Narayanasamy, Gilles Pokam, Brad Calder
ISCA
2005
IEEE
98views Hardware» more  ISCA 2005»
13 years 10 months ago
Techniques for Efficient Processing in Runahead Execution Engines
Runahead execution is a technique that improves processor performance by pre-executing the running application instead of stalling the processor when a long-latency cache miss occ...
Onur Mutlu, Hyesoon Kim, Yale N. Patt
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
13 years 10 months ago
RENO - A Rename-Based Instruction Optimizer
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
Vlad Petric, Tingting Sha, Amir Roth
ISCA
2005
IEEE
141views Hardware» more  ISCA 2005»
13 years 10 months ago
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...
Andreas Moshovos