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ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
13 years 11 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic
ISCA
2008
IEEE
134views Hardware» more  ISCA 2008»
13 years 11 months ago
Flexible Decoupled Transactional Memory Support
A high-concurrency transactional memory (TM) implementation needs to track concurrent accesses, buffer speculative updates, and manage conflicts. We present a system, FlexTM (FLE...
Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. ...
ISCA
2008
IEEE
165views Hardware» more  ISCA 2008»
13 years 11 months ago
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be m...
Lee Baugh, Naveen Neelakantam, Craig B. Zilles
ISCA
2008
IEEE
142views Hardware» more  ISCA 2008»
13 years 11 months ago
Improving NAND Flash Based Disk Caches
Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable spe...
Taeho Kgil, David Roberts, Trevor N. Mudge
ISCA
2008
IEEE
160views Hardware» more  ISCA 2008»
13 years 11 months ago
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
13 years 11 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
13 years 11 months ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda
ISCA
2008
IEEE
125views Hardware» more  ISCA 2008»
13 years 11 months ago
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....
ISCA
2008
IEEE
150views Hardware» more  ISCA 2008»
13 years 11 months ago
Fetch-Criticality Reduction through Control Independence
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matth...
ISCA
2008
IEEE
109views Hardware» more  ISCA 2008»
13 years 11 months ago
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and...
Shimin Chen, Michael Kozuch, Theodoros Strigkos, B...