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ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
10 years 6 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
10 years 6 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...
ISCA
2009
IEEE
201views Hardware» more  ISCA 2009»
10 years 6 months ago
A memory system design framework: creating smart memories
Amin Firoozshahian, Alex Solomatnikov, Ofer Shacha...
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
10 years 6 months ago
Ten ways to waste a parallel computer
Katherine A. Yelick
ISCA
2009
IEEE
178views Hardware» more  ISCA 2009»
10 years 6 months ago
Thread motion: fine-grained power management for multi-core systems
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
Krishna K. Rangan, Gu-Yeon Wei, David Brooks
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
10 years 6 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
10 years 6 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
10 years 6 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
10 years 6 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
10 years 6 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
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