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ISCA
2009
IEEE
161views Hardware» more  ISCA 2009»
13 years 11 months ago
AnySP: anytime anywhere anyway signal processing
In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world—a device that we...
Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. ...
ISCA
2009
IEEE
192views Hardware» more  ISCA 2009»
13 years 11 months ago
A case for bufferless routing in on-chip networks
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
Thomas Moscibroda, Onur Mutlu
ISCA
2009
IEEE
139views Hardware» more  ISCA 2009»
13 years 11 months ago
Reactive NUCA: near-optimal block placement and replication in distributed caches
Nikos Hardavellas, Michael Ferdman, Babak Falsafi,...
ISCA
2009
IEEE
180views Hardware» more  ISCA 2009»
13 years 11 months ago
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zh...
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
13 years 11 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
ISCA
2009
IEEE
123views Hardware» more  ISCA 2009»
13 years 11 months ago
InvisiFence: performance-transparent memory ordering in conventional multiprocessors
Colin Blundell, Milo M. K. Martin, Thomas F. Wenis...
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
13 years 11 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
ISCA
2009
IEEE
158views Hardware» more  ISCA 2009»
13 years 11 months ago
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applicatio...
Carlos Madriles, Pedro López, Josep M. Codi...